As complementary metal oxide semiconductor (CMOS) technology miniaturizes, reducing a stress influence is important in improving a device characteristic. In a semiconductor device having a small channel and a narrow width, threshold voltage and drain saturation current sensitively react to the layout of a semiconductor layer, which reduces impurity diffusion and increases carrier mobility under influence of physical stress from a shallow trench isolation (STI).
As the CMOS technology moves towards nano scale miniaturization, characteristics of a metal oxide semiconductor field effect transistor (MOSFET) are increasingly sensitively influenced by the layout pattern of a device.
A threshold voltage Vthi of the MOSFET, transconductance gm, and a saturation drain current Idsat represent different characteristics of a MOSFET for a semiconductor layer and a gate electrode of the same size in the MOSFET depending on the kind of STI and chemical vapor deposition (CVD) film.
To solve this problem, many efforts have been made. One of such efforts is to control a drive current using force (i.e., stress caused by compression and tension) applied to a gate electrode due to a CVD film characteristic, and to improve a stress influence using this drive current. However, since NMOS and pMOS drive currents act on each other in an opposite manner in reduction of a stress influence through adjustment of a CVD film layer, such mechanism is not sufficient for optimum reduction of the stress influence. Due to such characteristics, it is difficult to apply the related art to a nano scale reduction requiring a more precise device parameter. Also, this technology cannot solve a stress influence occurring in a predetermined fine pattern after set-up. Even when a drive current is controlled using an implantation method, transistors of an entire chip can be indispensably twisted.
This problem acts as a great obstacle in development of logic circuits or analog circuits of a sub-nano device that has lots of various layout patterns and requires accuracy.
Also, such a characteristic causes a crucial problem that a device parameter cannot be expressed as one parameter set when a spice or a model parameter is extracted.
It is estimated that one of most important reasons causing this problem is mechanical stress generated from an edge of an STI. Since the mechanical stress has a great influence on a device characteristic, it should be reduced.
To reduce a stress influence, a related art has improved device performance by improving electron mobility, hot carrier immunity, and dopant diffusion. Also, there is a report proposing a method of reducing STI stress as a primary method in terms of a junction leakage current increase and stress caused by crystal defects.
However, the present invention reduces a stress influence by modifying a layout pattern, i.e., a pattern design to solve problems indispensably occurring during a process and to achieve a device performance desired by a designer.
To improve this stress influence, patterns designed using three different methods are formed in a mask, and the formed patterns are checked during a silicon forming process.